1. Field
This disclosure relates generally to ESD protection of an integrated circuit, and more specifically, to ESD protection of an integrated circuit at a package level.
2. Related Art
Electrostatic Discharge (ESD) has been and continues to be a problem with integrated circuits. During ESD events potentially damaging voltages can develop across two conductive contacts of an integrated circuit. Much effort is spent to provide adequate ESD protection for the conductive contacts on an integrated circuit. A significant portion of the area used for the input/output circuitry is occupied by ESD protection. This on-chip ESD protection can add significant capacitance on input/output (I/O) conductive contacts, which can compromise the performance of the chip. One of the ways to reduce some of the space required for ESD protection on the integrated circuit and/or to increase the protection against ESD events while also reducing the capacitive load on input/output pins is to provide ESD protection at the package level. In such a case, ESD protection is incorporated in the package which contains the integrated circuit. Such ESD protection, however, is often difficult to achieve reliably and also may be costly to implement because of extensive additional package assembly processing.
Thus, there is a need for package level ESD protection that improves upon the issues described above.